The present disclosure relates to methods for fabricating a semiconductor device having a through-silicon via (TSV).
In recent years, a technique for forming small-size, large-capacity, and highly functional semiconductor devices by stacking a plurality of semiconductor devices having a through-silicon vias has been developed.
Through-silicon vias may be formed in semiconductor devices using several methods. For example, a via-first method forms a through-silicon via prior to forming the semiconductor element (such as a transistor) in the semiconductor wafer, and a via-last method forms the through-silicon via after forming the semiconductor element. In semiconductor devices utilized in devices such as an image sensor, the through-silicon via is often formed by the via-last method.
The following description of a conventional method of fabricating a semiconductor device having a through-silicon via formed by a via-last method refers to FIGS. 24-34. In the step shown in FIG. 24, a semiconductor wafer 5 including a non-illustrated semiconductor element on a top surface of a silicon substrate 1, serving as a semiconductor substrate and formed of silicon (Si); an interlayer insulating film 2 formed of silicon oxide (SiO2) on the top surface of the silicon substrate 1; pads 3 formed of a conductive material (such as aluminum) selected from a group of conductive materials including aluminum (Al), titanium (Ti), copper (Cu), nickel (Ni), and solder on the interlayer insulating film 2 and electrically connected to predetermined portions of the non-illustrated semiconductor element; and a passivation film 4, serving as a protective film, formed of silicon nitride (Si3N4) and configured to cover upper portions of the interlayer insulating film 2 and the pads 3.
In the step shown in FIG. 25, a resist mask (not illustrated) is formed on the passivation film 4 using a photolithography process, leaving exposed portions of the passivation film 4 corresponding to regions of the pads 3 where openings 7 are to be formed. Using the resist mask as a mask, the openings 7 extending to the pads 3 are formed by an anisotropic etching process. Thereafter, the resist mask is removed using a remover.
Subsequently, another resist mask 8A is formed on the passivation film 4 using a photo/lithography process, leaving exposed portions of the passivation film 4 corresponding to regions including the openings 7 where upper electrodes 9 are to be formed. Then, the openings 7 and the openings of the resist mask 8A are filled with a conductive material (such as nickel) by an electroplating method to form upper terminals 9, which are electrically connected to the pads 3.
In the step shown in FIG. 26, the resist mask 8A used for forming the upper terminals 9 is removed using a remover, and a support member II is bonded onto the upper terminals 9 and the passivation film 4 on the top surface side of the silicon substrate 1 using a bonding material 10.
In the step shown in FIG. 27, the bottom surface of the silicon substrate 1 is polished using a grinder, so that the silicon substrate 1 becomes a thin plate having a predetermined thickness (about 50 μm, for example).
In the step shown in FIG. 28, a bottom insulating film 13 of an insulating material (such as silicon oxide) is formed on the bottom surface of the polished silicon substrate 1 by a CVD (chemical vapor deposition) method. Thereafter, another resist mask 8B exposing portions of the bottom insulating film 13 corresponding to regions below the pads 3 where through-silicon vias (TSV) 15 are to be formed is formed on the bottom insulating film 13 by a photolithography process.
In the step shown in FIG. 29, the bottom insulating film 13 and the silicon substrate 1 are etched by an anisotropic etching process to form pilot holes extending to the interlayer insulating film 2 using the resist mask 8B formed in the step of FIG. 28 as a mask. Electrode-forming holes 16 extending to the pads 3 are formed. Using the same resist mask 8B as a mask, the interlayer insulating film 2 exposed to bottom portions of the pilot holes is etched by an anisotropic etching process using a different etching gas.
In the step shown in FIG. 30, the resist mask 8B formed in step of FIG. 28 is removed by a plasma ashing process, and an insulating material (such as silicon oxide) is deposited on the bottom insulating film 13 and the inner surfaces (i.e., the end and side surfaces) of the electrode-forming holes 16 by a CVD method, so that an electrode insulating film 18 covers the bottom insulating film 13 and the inner surfaces of the electrode-forming holes 16.
In the step shown in FIG. 31, the surfaces on the bottom of the silicon substrate 1 are etched by an anisotropic etching process to remove the electrode insulating film 18 formed on the bottom insulating film 13 and the end surfaces of the electrode-forming holes 16, while the electrode insulating film 18 covering the side surfaces of the electrode-forming holes 16 remains. A conductive material (such as titanium) is deposited by a sputtering process on the bottom insulating film 13, the pads 3 (the end surfaces of the electrode-forming holes 16), and the electrode insulating film 18 disposed on the side surfaces of the electrode-forming holes 16, thereby forming a barrier metal layer 20. Thereafter, a conductive material (such as copper) is deposited thereon by a sputtering process to form a seed metal layer 21, and a conductive material layer 15A of a conductive material (such as copper) is formed on the seed metal layer 21 using an electroplating method. In this way, the electrode-forming holes 16 are filled with the conductive material (such as copper).
In the step shown in FIG. 32, the barrier metal 20, the seed metal 21, and the conductive material layer 15A on the bottom insulating film 13 are removed by a CMP (chemical mechanical polishing) method. Through-silicon vias (TSV) 15 in the electrode-forming holes 16 are electrically connected to the pads 3.
Thereafter, a conductive material (such as titanium) is deposited by a sputtering process to form another barrier metal layer 23. Subsequently, a conductive material (such as copper) is deposited thereon by a sputtering process to form another seed metal layer 24. Another resist mask 8C having openings exposing portions of the seed metal layer 24 corresponding to regions including the through-silicon vias (TSV) 15 where lower electrodes 26 are to be formed is formed on the seed metal layer 24 by a photolithography process. The openings of the resist mask 8C are filled with a conductive material (such as nickel) by an electroplating method, so that lower terminals 26 are formed and are electrically connected to the through-silicon vias (TSV) 15.
In the step shown in FIG. 33, the resist mask 8C used for forming the lower terminals 26 is removed using a remover, and portions of the barrier metal layer 23 and the seed metal layer 24 are removed by a wet etching process to expose the bottom insulating film 13.
In the step shown in FIG. 34, the bonding material 10 is removed to separate the support member 11, thereby forming a semiconductor device 28. In this way, a semiconductor device having a through-silicon via (TSV) is formed using a conventional fabrication method.
A conventional via-first method of forming a through-silicon via (TSV) is disclosed in Japanese Laid-Open Patent Application No. 2007-180529 (refer to, for example, paragraphs [0034] to [0038], on pages 10 and 11, and FIGS. 3, 4 and 7), which is incorporated by reference. Prior to forming a semiconductor element in a semiconductor wafer, insulating rings are formed in portions of a semiconductor substrate where through-silicon vias (TSV) are to be formed, and the semiconductor element and a wiring layer are successively formed in the semiconductor substrate. Thereafter, the semiconductor wafer is divided into semiconductor chips, each having a semiconductor element and an insulating ring formed thereon, and the semiconductor chip is mounted on a mounting substrate. The bottom surface of the semiconductor chip is polished until the insulating ring is exposed, and an inorganic insulating film formed of silicon oxide or silicon nitride is formed on the bottom surface of the semiconductor chip. A resist mask having openings corresponding to the through-silicon via (TSV) forming regions is formed on the inorganic insulating film, and through holes are formed by a dry etching process, penetrating through the inorganic insulating film and the semiconductor substrate of the semiconductor chip and extending to contact plugs embedded in an insulating film of the wiring layer. Thereafter, the through holes are filled with metal using an electroplating process, thereby forming the through-silicon vias (TSV).
However, according to the above-described conventional via-last fabrication method, upon forming of the through-silicon via (TSV), the electrode-forming holes are formed so as to extend from the bottom insulating film formed on the bottom surface of the silicon substrate to the pads, and the electrode insulating film is formed so as to cover the inner surfaces of the electrode-forming holes. Thereafter, the electrode insulating film is removed from the end surfaces of the electrode-forming holes by an anisotropic etching process, and a conductive material is filled in the electrode-forming holes by an electroplating method, thereby forming through-silicon vias (TSV). Therefore, when the electrode insulating film is removed from the end surfaces of the electrode-forming holes by the anisotropic etching process, the electrode insulating film is often removed from the side surfaces of the electrode-forming holes. When a portion of the electrode insulating film is removed, the through-silicon vias (TSV) and the silicon substrate may be electrically short-circuited, and, thus, the quality of the semiconductor device may be reducted.
Moreover, though the technique of Japanese Laid-Open Patent Application No. 2007-180529 is one type of via-first method, such a via-first method may present a problem when a first company entrusts a second company with fabrication of a semiconductor wafer having a semiconductor element formed thereon. Specifically, the first company may need to rely on the second company to form the insulating ring or the like.